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HCC40105B HCF40105B
FIFO REGISTER
.I .3.EXPANDABLEI .STATUSI .RESETCAPABI .STANDARDI .QUI .5V,10V,AND15VPARAMETRI .I .100%TESTEDFORQUI .MEETSALLREQUI
DESCRIPTION
NDEPENDENT ASYNCHRONOUS INPUTS AND OUTPUTS STATE OUTPUTS N EITHER DIRECTION NDICATORS ON INPUT AND OUTPUT LITY ZED, SYMMETRICAL OUTPUT CHARACTERISTICS ESCENT CURRENT SPECIFIED AT 20V FOR HCC DEVICE C RATINGS NPUT CURRENT OF 100nA AT 18V AND 25C FOR HCC DEVICE ESCENT CURRENT REMENTS OF JEDEC TENTATIVE STANDARD No 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B" SERIES CMOS DEVICES"
READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output.
EY (Plastic Package)
F (Ceramic Package)
C1 (Chip Carrier) ORDER CODES : HCC40105BF HCF40105BEY HCF40105BC1
The HCC40105B (extended temperature range) and HCF40105B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package. The HCC/HCF40105B is a low-power first-in-first-out (FIFO) "elastic" storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A "1" signifies that the position's data is filled and a "0" denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the "0" state and sees a "1" in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0". The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATA-OUT
June 1989
PIN CONNECTIONS
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HCC/HCF40105B
FUNCTIONAL DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol V DD * Vi II Pto t Parameter Supply Voltage : HCC Types HC F Types Input Voltage DC Input Current (any one input) Total Power Dissipation (per package) Dissipation per Output Transistor for T o p = Full Package-temperature Range Operating Temperature : H CC Types H C F Types Storage Temperature Value - 0.5 to + 20 - 0.5 to + 18 - 0.5 to V DD + 0.5 10 200 100 - 55 to + 125 - 40 to + 85 - 65 to + 150 Unit V V V mA mW mW C C C
T op T stg
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability. * All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol V DD VI Top Parameter Supply Voltage : HC C Types H CF Types Input Voltage Operating Temperature : H CC Types H C F Types Value 3 to 18 3 to 15 0 to V DD - 55 to + 125 - 40 to + 85 Unit V V V C C
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HCC/HCF40105B
LOGIC DIAGRAM
TIMING DIAGRAM
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HCC/HCF40105B
STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)
Symbol IL Parameter Quiescent Current Test Conditions VO |I O | V D D T L o w* (V) (A) (V) Min. Max. 0/ 5 5 5 0/10 10 10 0/15 15 20 0/20 20 100 0/ 5 5 20 0/10 10 40 0/15 15 80 0/ 5 <1 5 4.95 0/10 <1 10 9.95 0/15 <1 15 14.95 5/0 <1 5 0.05 10/0 <1 10 0.05 15/0 <1 15 0.05 0.5/4.5 < 1 5 3.5 1/9 <1 10 7 1.5/13.5 < 1 15 11 4.5/0.5 < 1 5 1.5 9/1 <1 10 3 13.5/1.5 < 1 15 4 0/ 5 2.5 5 -2 0/ 5 4.6 5 - 0.64 0/10 9.5 10 - 1.6 0/15 13.5 15 - 4.2 0/ 5 2.5 5 - 1.53 0/ 5 4.6 5 - 0.52 0/10 9.5 10 - 1.3 0/15 13.5 15 - 3.6 0/ 5 0.4 5 0.64 0/10 0.5 10 1.6 0/15 1.5 15 4.2 0/ 5 0.4 5 0.52 0/10 0.5 10 1.3 0/15 1.5 15 3.6 VI (V) 18 Any Input 15 0/18 0/15 Any Input 18 15 0.3 0.4 1.0 10 - 5 0.3 10 - 4 0.4 10 - 4 1.0 5 7.5 1 12 7.5 A pF 0.1 Value 25 C Min. Typ. Max. 0.04 5 0.04 10 0.04 20 0.08 100 0.04 20 0.04 40 0.04 80 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 - 1.6 - 3.2 - 0.51 - 1 - 1.3 - 2.6 - 3.4 - 6.8 - 1.36 - 3.2 - 0.44 - 1 - 1.1 - 2.6 - 3.0 - 6.8 0.51 1 1.3 2.6 3.4 6.8 0.44 1 1.1 2.6 3.0 6.8 10 - 5 0.1 T Hi g h * Min. Max. 150 300 600 3000 150 300 600 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 - 1.15 - 0.36 - 0.9 - 2.4 - 1.1 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 0.36 0.9 2.4 1 A Unit
HCC Types
A
HCF Types V OH Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Output Drive Current
V
V OL
V
V IH
V
V IL
V
I OH
HCC Types
mA
HCF Types I OL Output Sink Current
HCC Types HCF Types
mA
I IH , I IL
HCF 0/15 Types I O H,I O L ** 3-State HCC 0/18 Output Types Leakage HCF 0/15 Current Types Input Capacitance CI
* *
Input Leakage Current
HCC Types 0/18
TLo w = - 55C for HCC device : - 40C for HCF device. THigh = + 125C for HCC device : + 85C for HCF device. The Noise Margin for both "1" and "0" level is : 1V min. with VDD = 5V, 2V min. with VDD = 10V, 2.5 V min. with VDD = 15V. * * Forced output disable.
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HCC/HCF40105B
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb = 25 C, C L = 50 pF, R L = 200 k, typical temperature coefficient for all V D D values is 0.3 %/C, all input rise and fall time = 20 ns)
Symbol t P HL Parameter Propagation Delay Time Shift-out or Reset to Data-out Ready Propagation Delay Time Shift-in to Data-in Ready Test Conditions V D D (V) Min. 5 10 15 5 10 15 t P ZH, t P ZL Propagation Delay Time 3-state Control to Data-out 5 10 15 t P HZ , t P L Z Propagation Delay Time 3-State Control to Data-out 5 10 15 tPLH Ripple-through Delay Input to Output 5 10 15 t THL , t TL H Transition Time 5 10 15 fI Shift-in or Shift-out Rate 5 10 15 t WH Shift-in Pulse Width 5 10 15 t WL Shift-out Pulse Width 5 10 15 tr Shift-in or Shift-out Rise Time 5 10 15 tf Shift-in Fall Time 5 10 15 tf Shift-out Fall Time 5 10 15 tse tup Data Setup Time 5 10 15 0 0 0 ns 200 80 60 360 160 100 Value Typ. 185 90 65 160 65 45 140 60 40 100 50 40 2 1 0.7 100 50 40 1.5 3 4 100 40 30 180 80 50 15 15 15 15 15 15 15 5 5 s s s ns ns Max. 370 180 130 320 130 90 280 120 80 200 100 80 4 2 1.4 200 100 80 3 6 8 MHz ns s ns ns ns ns Unit
t P HL
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HCC/HCF40105B
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Symbol t h o ld Parameter Data Hold Time Test Conditions V D D (V) Min. 5 10 15 t WL Data-in Ready Pulse Width 5 10 15 t WL Data-out Ready Pulse Width 5 10 15 t WH Master Reset Pulse Width 5 10 15 200 90 60 350 150 120 Value Typ. 175 75 60 260 100 70 220 90 665 100 45 30 ns 520 120 140 440 180 130 ns ns ns Max. Unit
Output Low (sink) Current Characteristics.
Output High (source) Current Characteristics.
Typical Transition Time vs. Load Capacitance.
Typical Dynamic Power Dissipation vs. Frequency.
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HCC/HCF40105B
TEST CIRCUITS Quiescent Device Current. Input Voltage.
Input Leakage Current.
Dynamic Power Dissipation.
TYPICAL APPLICATIONS EXPANSION, 4 BITS-WIDE-BY-16 N-BITS LONG.
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HCC/HCF40105B
EXPANSION, 8 BITS-WIDE-BY-16 N-BITS LONG.
APPLICATIONS INFORMATION LOADING DATA Data can be entered whenever the DATA-IN READY (DIR) flag is high, by a low to high transition on the SHIFT-IN (SI) input. This input must go low momentarily before the next word is accepted by the FIFO. The DIR flag will go low momentarily, until the data have been transferred tothe second location. The flag will remain low when all 16-word locations are filled with valid data, and further pulses on the SI input will be ignored until DIR goes high. UNLOADING DATA As soon as the first word has rippled to the output, DATA-OUT READY (DOR) goes high, and data can be removed by afalling edge on theSO input. This falling edge causes the DOR signal to go low while the word on the output is dumped and the next word moves to the output. As long as valid data are available in the FIFO, the DOR signal will go high again signifying that the next word is ready at the output. When the FIFO is empty, DOR will remain low, and any further commands will be ignored until a "1" marker ripples down to the last control register, when DOR goes high. Unloading of data is inhibited while the 3state control input is high. The 3-state control signal should not be shifted from high to low (data outputs turned on)while the SHIFT-OUT is at logic 0. This level change would cause the first word to be shifted out (unloaded) immediately and the data to be lost. CASCADING The HCC/HCF40105B can be cascaded to form longer registers simply by connecting the DIR to SO and DOR to SI. In the cascaded mode, a MASTER RESET pulse must be applied after the supply voltage is turned on. For words wider than 4 bits, the DIR and the DOR outputs must be gated together with AND gates. Their outputs drive the SI and SO inputs in parallel, if expanding is done in both directions. 3-STATE OUTPUTS In order to facilitate data busing, 3-state outputs are provided on the data output lines, while the load condition of the register can be detected by the state of the DOR output. MASTER RESET A high on the MASTER RESET (MR) sets all the control logic marker bits to "0". DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be superseded when the first word is loaded.
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HCC/HCF40105B
Plastic DIP14 MECHANICAL DATA
mm MIN. a1 B b b1 D E e e3 F I L Z 1.27 3.3 2.54 0.050 8.5 2.54 15.24 7.1 5.1 0.130 0.100 0.51 1.39 0.5 0.25 20 0.335 0.100 0.600 0.280 0.201 1.65 TYP. MAX. MIN. 0.020 0.055 0.020 0.010 0.787 0.065 inch TYP. MAX.
DIM.
P001A
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HCC/HCF40105B
Ceramic DIP14/1 MECHANICAL DATA
mm MIN. A B D E e3 F G H L M N P Q 7.8 2.29 0.4 1.17 0.22 1.52 0.38 15.24 2.79 0.55 1.52 0.31 2.54 10.3 8.05 5.08 0.307 0.090 0.016 0.046 0.009 0.060 3.3 0.015 0.600 0.110 0.022 0.060 0.012 0.100 0.406 0.317 0.200 TYP. MAX. 20 7.0 0.130 MIN. inch TYP. MAX. 0.787 0.276
DIM.
P053C
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HCC/HCF40105B
PLCC20 MECHANICAL DATA
mm MIN. A B D d1 d2 E e e3 F G M M1 1.27 1.14 7.37 1.27 5.08 0.38 0.101 0.050 0.045 9.78 8.89 4.2 2.54 0.56 8.38 0.290 0.050 0.200 0.015 0.004 TYP. MAX. 10.03 9.04 4.57 MIN. 0.385 0.350 0.165 0.100 0.022 0.330 inch TYP. MAX. 0.395 0.356 0.180
DIM.
P027A
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HCC/HCF40105B
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
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